KUMAR, B. R.; KUMAR, P.; REDDY, K. N.; ALEX, E. J. Low – Power TSPC Flip-Flop with Auto-Gated Clock Gating, Power Gating and Redundant-Transition Suppression. Journal of Electronic & Information Systems, [S. l.], v. 7, n. 2, p. 25–37, 2025. DOI: 10.30564/jeis.v7i2.10818. Disponível em: https://journals.bilpubgroup.com/index.php/jeis/article/view/10818. Acesso em: 8 sep. 2025.