SYAMALA, B.; MUTHUSAMY, T. An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate. Journal of Electronic & Information Systems, [S. l.], v. 5, n. 1, p. 26–35, 2023. DOI: 10.30564/jeis.v5i1.5574. Disponível em: https://journals.bilpubgroup.com/index.php/jeis/article/view/5574. Acesso em: 21 nov. 2024.