High-Throughput CBC Mode Crypto Circuit
The objective of this study is to investigate a high-throughput cipher-block chaining (CBC) mode crypto circuit, which can be embedded in commercial home gateways or switches/routers. Concurrently, the area efficiency of block ciphers can be improved as well. However, the CBC mode encounters the problem of data dependency. To solve this issue, a data scheduling mechanism of network packets is proposed to eliminate the data dependency of input data for CBC mode pipelined crypto engines. The proposed CBC mode architecture can be applied to advanced encryption standards (AES), triple data encryption standards (3DES), and other block ciphers. In addition, to increase the throughput, deeply pipelined AES-CBC and 3DES-CBC circuits with balanced paths are proposed. With the proposed scheduling and pipelined circuits, the authors can effectively encrypt the packet data of multiple network channels at the same time. Using the proposed architecture, throughputs of 137.8 and 44.75 Gbps using a copy of pipelined AES-CBC and 3DES-CBC circuits can be achieved in TSMC 45 nm and TSMC 130 nm processes, respectively.
Keywords:3DES-CBC, AES-CBC, Area efficiency, ASIC, FPGA, Security, Throughput
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Copyright © 2023 Kai-Chun Chang, You-Tun Teng, Wen-Long Chin
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