-
2018
-
1958
-
1718
-
1509
-
1498
High-Throughput CBC Mode Crypto Circuit
DOI:
https://doi.org/10.30564/ese.v5i1.5636Abstract
The objective of this study is to investigate a high-throughput cipher-block chaining (CBC) mode crypto circuit, which can be embedded in commercial home gateways or switches/routers. Concurrently, the area efficiency of block ciphers can be improved as well. However, the CBC mode encounters the problem of data dependency. To solve this issue, a data scheduling mechanism of network packets is proposed to eliminate the data dependency of input data for CBC mode pipelined crypto engines. The proposed CBC mode architecture can be applied to advanced encryption standards (AES), triple data encryption standards (3DES), and other block ciphers. In addition, to increase the throughput, deeply pipelined AES-CBC and 3DES-CBC circuits with balanced paths are proposed. With the proposed scheduling and pipelined circuits, the authors can effectively encrypt the packet data of multiple network channels at the same time. Using the proposed architecture, throughputs of 137.8 and 44.75 Gbps using a copy of pipelined AES-CBC and 3DES-CBC circuits can be achieved in TSMC 45 nm and TSMC 130 nm processes, respectively.
Keywords:
3DES-CBC; AES-CBC; Area efficiency; ASIC; FPGA; Security; ThroughputReferences
[1] Li, A., Gong, C., Huang, X., et al., 2022. Overview of key technologies for water-based automatic security marking platform. Electrical Science & Engineering. 4(1), 30-40.
[2] Chin, W.L., Tseng, C.L., Tsai, C.S., et al. (editors), 2012. Channel-based detection of primary user emulation attacks in cognitive radios. 2012 IEEE 75th Vehicular Technology Conference (VTC Spring); 2012 May 6-9; Yokohama. New York: IEEE.
[3] Le, T.N., Chin, W.L., Kao, W.C., 2015. Cross-layer design for primary user emulation attacks detection in mobile cognitive radio networks. IEEE Communications Letters. 19(5), 799-802.
[4] Chin, W.L., 2019. On the noise uncertainty for the energy detection of OFDM signals. IEEE Transactions on Vehicular Technology. 68(8), 7593-7602.
[5] Chin, W.L., Kao, C.W., Chen, H.H., et al., 2013. Iterative synchronization-assisted detection of OFDM signals in cognitive radio systems. IEEE Transactions on Vehicular Technology. 63(4), 1633-1644.
[6] Chin, W.L., Lin, Y.H., Chen, H.H., 2016. A framework of machine-to-machine authentication in smart grid: A two-layer approach. IEEE Communications Magazine. 54(12), 102-107.
[7] Chin, W.L., Le, T.N., Tseng, C.L., 2015. Authentication scheme for mobile OFDM based on security information technology of physical layer over time-variant and multipath fading channels. Information Sciences. 321, 238-249. DOI: https://doi.org/10.1016/j.ins.2015.01.040
[8] Yoosuf, M.S., Muralidharan, C., Shitharth, S., et al., 2022. FogDedupe: A Fog-Centric deduplication approach using multi-key homomorphic encryption technique. Journal of Sensors. 6759875. DOI: https://doi.org/10.1155/2022/6759875
[9] Jin, Z., Jia, W.K., 2022. P3FA: Unified unicast/multicast forwarding algorithm for high-performance router/switch. IEEE Transactions on Consumer Electronics. 68(4), 327-335.
[10] Chin, W.L., Chen, S.G., 2009. IEEE 1588 clock synchronization using dual slave clocks in a slave. IEEE Communications Letters. 13(6), 456-458.
[11] Cho, E.A., Moon, C.J., Baik, D.K., 2008. Home gateway operating model using reference monitor for enhanced user comfort and privacy. IEEE Transactions on Consumer Electronics. 54(2), 494-500.
[12] Kim, H.W., Lee, S., 2004. Design and implementation of a private and public key crypto processor and its application to a security system. IEEE Transactions on Consumer Electronics. 50(1), 214-224.
[13] Kim, D.S., Lee, S.Y., Kim, B.S., et al., 2008. On the design of an embedded biometric smart card reader. IEEE Transactions on Consumer Electronics. 54(2), 573-577.
[14] National Institute of Standards and Technology, 2001. Specification for the advanced encryption standard (AES), FIPS PUB197 [Interenet]. Available from: https://nvlpubs.nist.gov/nistpubs/fips/nist.fips.197.pdf
[15] Singha, T.B., Palathinkal, R.P., Ahamed, S.R. (editors), 2020. Implementation of AES using composite field arithmetic for IoT applications. 2020 Third ISEA Conference on Security and Privacy (ISEA-ISAP); 2020 Feb 27-Mar 1; Guwahati. New York: IEEE. p. 115-121.
[16] Janveja, M., Paul, B., Trivedi, G., et al. (editors), 2020. Design of efficient AES architecture for secure ECG signal transmission for low-power IoT applications. 2020 30th International Conference Radioelektronika (RADIOELEKTRONIKA); 2020 Apr 15-16; Bratislava. New York: IEEE. p. 1-6.
[17] Chin, W.L., Ko, H.A., Chen, N.W., et al., 2023. Securing NFV/SDN IoT using Vnfs over a compute-intensive hardware resource in NFVI. IEEE Network. 1-8. DOI: https://doi.org/10.1109/MNET.135.2200558
[18] Zhang, X., Parhi, K.K., 2004. High-speed VLSI architectures for the AES algorithm. IEEE Transactions on very Large Scale Integration (VLSI) Systems. 12(9), 957-967.
[19] Teng, Y.T., Chin, W.L., Chang, D.K., et al., 2021. VLSI architecture of S-Box with high area efficiency based on composite field arithmetic. IEEE Access. 10, 2721-2728.
[20] Manjith, B.C. (editor), 2019. Improving overall parallelism in AES accelerator using BRAM and multiple input blocks. 2019 Innovations in Power and Advanced Computing Technologies (i-PACT); 2019 Mar 22-23; Vellore. New York: IEEE.
[21] Ueno, R., Morioka, S., Miura, N., et al., 2019. High throughput/gate AES hardware architectures based on datapath compression. IEEE Transactions on Computers. 69(4), 534-548.
[22] Mathew, S.K., Sheikh, F., Kounavis, M., et al., 2011. 53 Gbps native GF composite-field AES-encrypt/decrypt accelerator for content-protection in 45 nm high-performance microprocessors. IEEE Journal of Solid-State Circuits. 46(4), 767-776.
[23] American National Standards Institute, Inc., 1998. Triple Data Encryption Algorithm Modes of Operation, ANSI X9.52 [Internet]. Available from: https://standards.globalspec.com/std/546836/X9.52
[24] Khan, Z., Benaissa, M., 2015. Throughput/area-efficient ECC processor using montgomery point multiplication on FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs. 60(11), 1078-1082.
[25] Lim, Y.W. (editor), 2000. Efficient 8-cycle DES implementation. Proceedings of Second IEEE Asia Pacific Conference on ASICs; 2000 Aug 30-31; Cheju. New York: IEEE. p. 175-178.
[26] Zeebaree, S.R., 2020. DES encryption and decryption algorithm implementation based on FPGA. Indonesian Journal of Electrical Engineering and Computer Science. 18(2), 774-781.
[27] Fu, T., Li, S. (editors), 2017. A 3DES ASIC implementation with feedback path in the CBC mode. 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC); 2017 Oct 18-20; Hsinchu. New York: IEEE. p. 1-2.
[28] He, Y., Li, S. (editors), 2017. A 3DES implementation especially for CBC feedback loop mode. 2017 IEEE International Symposium on Circuits and Systems (ISCAS); 2017 Sep 28; Baltimore. New York: IEEE. p. 1-4.
[29] Wee, C.M., Sutton, P.R., Bergmann, N.W., et al. (editors), 2006. VPN acceleration using reconfigurable system-on-chip technology. 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines; 2006 Dec 11; Napa, CA. New York: IEEE. p. 281-282.
[30] Oukili, S., Bri, S. (editors), 2017. High speed efficient advanced encryption standard implementation. 2017 International Symposium on Networks Computers and Communications (ISNCC); 2017 May 16-18; Marrakech. New York: IEEE. p. 1-4.
[31] Kouzehzar, H., Moghadam, M.N., Torkzadeh, P. (editors), 2018. A high data rate pipelined architecture of AES encryption/decryption in storage area networks. Iranian Conference on Electrical Engineering (ICEE); 2018 May 8-10; Mashhad. New York: IEEE. p. 23-28.
Downloads
How to Cite
Issue
Article Type
License
Copyright © 2023 Kai-Chun Chang, You-Tun Teng, Wen-Long Chin
This is an open access article under the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) License.