Low – Power TSPC Flip-Flop with Auto-Gated Clock Gating, Power Gating and Redundant-Transition Suppression

Abstract

An advanced low-power True Single Phase Clock (TSPC) flip-flop design leveraging a synergistic integration of three power-saving techniques: auto-gated clock gating, power gating, and redundant-transition suppression. The proposed architecture targets both dynamic and leakage power reduction in sequential circuits without sacrificing speed or timing integrity. Auto-gated clock gating dynamically disables the clock signal when input data remains stable, eliminating unnecessary switching activity. Power gating is employed to disconnect the power supply to idle flip-flop stages during prolonged inactivity, significantly reducing static leakage current. Additionally, redundant-transition suppression logic prevents internal node toggling in response to non-transitioning inputs, further minimizing dynamic power dissipation. These techniques are seamlessly embedded within the TSPC structure, preserving its inherent advantages such as single-phase clock operation and high-speed performance. The design is implemented and verified through post-layout simulations in a standard CMOS technology, demonstrating substantial improvements in energy efficiency compared to conventional TSPC and other existing low-power flip-flop designs. Results indicate significant reductions in both active and standby power consumption, achieving superior energy-delay product metrics. The proposed flip-flop is particularly well-suited for high-performance digital systems operating under stringent energy constraints, such as portable and battery-powered devices. By intelligently managing clock and power resources while maintaining robust functionality, this design offers a practical and scalable solution for next-generation energy-efficient integrated circuits.