Signal and Power Integrity Challenges for High Density System-on-Package
AbstractAs the increasing desire for more compact, portable devices outpaces Moore’s law, innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself, as the case for system-on-package (SoP), has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining, let alone improving, reliability and performance. The fundamental signal, power, and thermal integrity issues are discussed in detail, along with published techniques from around the industry to mitigate these issues in SoP applications.
Keywords:System on package (SoP), System in package (SiP), System on chip (SoC), Through silicon via (TSV), Signal integrity, Power integrity, Thermal integrity
 Patel, D., 2020. Apple’s A14 packs 134 million transistors/mm², but falls short of TSMC’s density claims. https://semianalysis.com/apples-a14-packs-134-million-transistors-mm2-but-falls-far-short-oftsmcs-density-claims/. (Accessed 26 March 2022)
 Dai, W.W., 2016. Historical perspective of system in package (SiP). IEEE Circuits and Systems Magazine. 16(2), 50-61.DOI: https://doi.org/10.1109/MCAS.2016.2549949
 Rinebold, K., Felton, K., 2017. Designing and Integrating MCM/SiP Packages into Systems PCBs. https://www.3dincites.com/wp-content/uploads/mentorpaper_101401.pdf. (Accessed 26 March 2022).
 Lian, F., Wang, D., Chiu, R., et al., 2019. Innovative packaging solutions of 3D integration and system in package for IoT/wearable and 5G application. IEEE 21st Electronics Packaging Technology Conference (EPTC). pp. 515-518. DOI: https://doi.org/10.1109/EPTC47984.2019.9026573
 Elisabeth, S., 2019. Advanced RF packaging technology trends, from WLP and 3D integration to 5G and mmwave applications. International Wafer Level Packaging Conference (IWLPC) pp. 1-5.DOI: https://doi.org/10.23919/IWLPC.2019.8914089
 Wase, Y.S., Li, F., 2017, Technology review of system in package. In Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT). pp. 1-20.
 Tummala, R.R., 2004. SOP: what is it and why? A new microsystem-integration technology paradigm-Moore’s law for system integration of miniaturized convergent systems of the next decade. IEEE Transactions on Advanced Packaging. 27(2), 241-249.DOI: https://doi.org/10.1109/TADVP.2004.830354
 Ulrich, R.K., Brown, W.D., 2006. Advanced Electronic Packaging, IEEE. Ch.14. DOI: https://doi.org/10.1109/9780471754503.ch14
 Carchon, G., Vaesen, K., Brebels, S., et al., 2001. Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits. Transactions on Components and Packaging Technologies. 24(3), 510-519. DOI: https://doi.org/10.1109/6144.946500
 Foure, J., Dravet, A., Cazenave, J., et al., 1995. Mixed technologies for microwave multichip module (MMCM) applications-a review. IEEE NTC,Conference Proceedings Microwave Systems Conference. pp. 73-81. DOI: https://doi.org/10.1109/NTCMWS.1995.522865
 Shafique, M.F., Robertson, I.D., 2015. A two-stage process for laser prototyping of microwave circuits in LTCC technology. IEEE Transactions on Components, Packaging and Manufacturing Technology. 5(6), 723-730. DOI: https://doi.org/10.1109/TCPMT.2015.2434273
 Li, X., Gu, L., Wu, Z., 2008. (INVITED) High-performance RF passives using post-CMOS MEMS techniques for RF SoC. IEEE Radio Frequency Integrated Circuits Symposium. pp. 163-166. DOI: https://doi.org/10.1109/RFIC.2008.4561409
 Jun, H., Cho, J., Lee, K., et al., 2017. HBM (High Bandwidth Memory) DRAM technology and architecture. IEEE International Memory Workshop (IMW). pp. 1-4.DOI: https://doi.org/10.1109/IMW.2017.7939084
 Venkatesan, S., Aoulaiche, M., 2018. Overview of 3D NAND technologies and outlook. Non-Volatile Memory Technology Symposium (NVMTS). pp. 1-5.
 Apriyana, A.A., Ye, L., Seng, T.C., 2019. TSV with embedded capacitor for ASIC-HBM power and signal integrity improvement. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). pp. 1-2. DOI: https://doi.org/10.1109/S3S46989.2019.9320698
 Tseng, C.F., Liu, C.S., Wu, C.H., et al., 2016. InFO (Wafer Level Integrated Fan-Out) Technology. IEEE 66th Electronic Components and Technology Conference (ECTC). pp. 1-6.DOI: https://doi.org/10.1109/ECTC.2016.65
 You, S.H., Jeon, S., Oh, D., et al., 2018. Advanced fan-out package SI/PI/thermal performance analysis of novel RDL packages. IEEE 68th Electronic Components and Technology Conference (ECTC). pp. 1295-1301. DOI: https://doi.org/10.1109/ECTC.2018.00199
 Wan, L., 2018. SiP/SoP technology and its implementation. International Conference on Electronic Packaging Technology & High Density Packaging. pp. 1-3.DOI: https://doi.org/10.1109/ICEPT.2008.4606942
 Zhou, L., Feng, W., Wang D., et al., 2020. A compact millimeter-wave frequency conversion SOP (System on Package) module based on LTCC technology. IEEE Transactions on Vehicular Technology. 69(6), 5923-5932.DOI: https://doi.org/10.1109/TVT.2020.2989451
 Craton, M.T., Konstantinou, X., Albrecht, J.D., et al., 2021. Additive manufacturing of a W-band System-on-Package. IEEE Transactions on Microwave Theory and Techniques. 69(9), 4191-4198.DOI: https://doi.org/10.1109/TMTT.2021.3076066
 Georgiadis, A., Tentzeris, M., 2019. Achieving fully autonomous system-on-package designs: an embedded-on-package 5G energy harvester within 3D printed multilayer flexible packaging structures. IEEE MTT-S International Microwave Symposium (IMS). pp. 1375-1378.DOI: https://doi.org/10.1109/MWSYM.2019.8700931
 Johnson, J., Graham, M., 1993. High-Speed Digital Design: A handbook of black magic. Prentice Hall, Upper Saddle River, NJ.
 Palermo, S., 2021. Termination, TX driver, & multiplexer circuits. ECEN 720. Class Lecture, School of Electrical and Computer Engineering, Texas A&M University. College Station.
 Bogatin, E., 2018. Signal and Power Integrity - Simplified. Prentice Hall.
 Qualcomm. Snapdragon system-in-package. https://www.qualcomm.com/products/snapdragon-system-package. (Accessed 27 March 2022)
 Yang, Z., Gao, Y., Li, S., et al., 2021. Research on SiP signal integrity based on Ansys SIwave in wearable medical systems. 22nd International Conference on Electronic Packaging Technology (ICEPT). pp.1-4. DOI: https://doi.org/10.1109/ICEPT52650.2021.9567976
 Vasudevan, K., 2010. Digital communications and signal processing. Universities Press, Second edition.
 Wang, L., Zhang, Y., Zhang, G, et al, 2010. Power integrity analysis for high-speed PCB. First International Conference on Pervasive Computing, Signal Processing and Applications. pp. 414-418. DOI: https://doi.org/10.1109/PCSPA.2010.106
 Chandana, M., Mervin, J., Selvakumar, D., 2015. Power integrity analysis for high performance design. International Conference on Control, Electronics, Renewable Energy and Communications (ICCEREC). pp. 48-53. DOI: https://doi.org/10.1109/ICCEREC.2015.7337052
 Yoo, J., Im, Y., Lee, H., et al., 2020. Impact of Chip, Package, and Set Design on Transient Temperature in Mobile Application. 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm). pp. 229-235.DOI: https://doi.org/10.1109/ITherm45881.2020.9190945
 Mathur, R., Chao, C.J., Liu, R., et al., 2020. Thermal analysis of a 3D stacked high-performance commercial microprocessor using face-to-face wafer bonding technology. IEEE 70th Electronic Components and Technology Conference (ECTC). pp. 541-547.DOI: https://doi.org/10.1109/ECTC32862.2020.00091
 Micron Technology, Inc., 2018. High bandwidth memory with ECC. HMB2E Datasheet. https://media-www. micron.com/-/media/client/global/documents/products/data-sheet/dram/hbm2e/8gb_and_16gb_hbm2e_dram. pdf?rev=dbfcf653271041a497e5f1bef1a169ca. (Accessed 27 March 2022)
 Kim, S.K., Oh, D.S., Hwang, S., et al., 2019. Electrical and thermal co-analysis of thermally efficient SiP for high performance applications. Electrical Design of Advanced Packaging and Systems (EDAPS). pp. 1-3. DOI: https://doi.org/10.1109/EDAPS47854.2019.9011675
 Zumbühl, D., 2018. Magnetic cooling of nanoelectronic chips. Tech Briefs, University of Basel, Switzerland. https://www.techbriefs.com/component/content/article/tb/pub/briefs/electronics-and-computers/28564. (Accessed 27 March 2022)
 Bahiraei, M., Heshmatian, S., 2018. Electronics cooling with nanofluids: a critical review. Energy Conversion and Management. 172, 438-456. DOI: https://doi.org/10.1016/j.enconman.2018.07.047
How to Cite
Copyright © 2022 Nathan Totorica, Feng Li
This is an open access article under the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) License.