Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

Authors

  • Pooja Srivastava

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India

  • Aditi Upadhyaya

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India

  • Shekhar Yadav

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India

  • C.M.S. Negi

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India

DOI:

https://doi.org/10.30564/ssid.v5i2.6075
Received: 19 November 2023 | Revised: 30 December 2023 | Accepted: 3 January 2024 | Published Online: 18 January 2024

Abstract

The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance, JLFET emerges as a promising alternative to CTs. Notably, JLFET lacks junctions and doping concentration gradients. In this study, the authors have conducted a comprehensive analysis and performance evaluation of JLFET and CTs, specifically in the context of low-power applications. Various performance parameters of JLFET, including SS, DIBL, transconductance, output conductance, and Ion/Ioff, have been assessed. The findings indicate that JLFET exhibits reduced susceptibility to SCEs compared to CTs and demonstrates exceptional current driving capability.

Keywords:

Short channel effects, Drain-induced barrier lowering, Subthreshold slope, Gate-all-around junction less FET, Device simulation

References

[1] Moore, G.E., 1975. Progress in digital integrated electronics. Technical Digest. 21, 11–13.

[2] Colinge, J.P., Lee, C.W., Afzalian, A., et al., 2010. Nanowire transistors without junctions. Nature Nanotechnology. 5, 225–229. DOI: https://doi.org/10.1038/nnano.2010.15

[3] Ranka, D., Rana, A.K., Yadav, R.K., et al., 2011. Performance evaluation of FD-SOI MOSFETs for different metal gate work function. arXiv preprint arXiv:1104.0824. DOI: https://doi.org/10.48550/arXiv.1104.0824

[4] Colinge, J.P. (editor), 2012. Junctionless transistors. 2012 IEEE International Meeting for Future of Electron Devices, Kansai; 2012 May 9-11; Suita, Japan. New York: IEEE. DOI: https://doi.org/10.1109/IMFEDK.2012.6218561

[5] Gnani, E., Gnudi, A., Reggiani, S., et al., 2008.Quasi-ballistic transport in nanowire field-effect transistors. IEEE Transactions on Electron Devices. 55(11), 2918–2930. DOI: https://doi.org/10.1109/TED.2008.2005178

[6] Gnani, E., Gnudi, A., Reggiani, S., et al., 2008. Band effects on the transport characteristics of ultrascaled snw-fets. IEEE Transactions on Nanotechnology. 7(6), 700–709. DOI: https://doi.org/10.1109/TNANO.2008.2005777

[7] Lenzi, M., Palestri, P., Gnani, E., et al., 2008. Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltz-mann transport equation. IEEE Transactions on Electron Devices. 55(8), 2086–2096. DOI: https://doi.org/10.1109/TED.2008.926230

[8] Poli, S., Pala, M.G., Poiroux, T., 2009. Full quantum treatment of remote Coulomb scattering in silicon nanowire FETs. IEEE Transactions on Electron Devices. 56(6), 1191–1198. DOI: https://doi.org/10.1109/TED.2009.2019380

[9] Han, M.H., Chang, C.Y., Jhan, Y.R., et al., 2013. Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis. IEEE Electron Device Letters. 34(2), 157–159. DOI: https://doi.org/10.1109/LED.2012.2229105

[10] Baruah, R.K., Paily, R.P., 2013. A dual-material gate junctionless transistor with high-k spacer for enhanced analog performance. IEEE Transactions on Electron Devices. 61(1), 123–128. DOI: https://doi.org/10.1109/TED.2013.2292852

[11] Solankia, T., Parmar, N. (editors), 2011. A review paper: A comprehensive study of Junctionless transistor. National Conference on Recent Trends in Engineering & Technology; 2011 May 13–14; Gujarat, India.

[12] Merad, F., Guen-Bouazza, A., 2020. DC performance analysis of a 20 nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor. International Journal of Electrical and Computer Engineering. 10(4), 4043–4052.DOI: https://doi.org/10.11591/ijece.v10i4.pp4043-4052

[13] Lee, C.W., Afzalian, A., Yan, R., et al. (editors), 2009. Junctionless MuGFETs. Proceedings of EUROSOI Conference; 2009 Jan 1; Goteborg, Sweden. p. 21–22.

[14] Lee, C.W., Borne, A., Ferain, I., et al., 2010. High-temperature performance of silicon junctionless MOSFETs. IEEE Transactions on Electron Devices. 57(3), 620–625. DOI: https://doi.org/10.1109/TED.2009.2039093

[15] Ghosh, S., Jana, A., Agnihotri, A.K., et al. (editors), 2022. DC and analog/RF performance comparison of renovated GAA JLFET structures. 2022 IEEE VLSI Device Circuit and System (VLSI DCS); 2022 Feb 26–27; Kolkata, India. New York: IEEE. p. 80–84. DOI: https://doi.org/10.1109/VLSIDCS53788.2022.9811488

[16] Lee, C.W., Ferain, I., Afzalian, A., et al., 2010. Performance estimation of junctionless multi gate transistors. Solid-State Electronics. 54(2), 97–103. DOI: https://doi.org/10.1016/j.sse.2009.12.003

[17] Kamath, A., Chen, Z.X., Shen, N., et al., 2013. Junctionless CMOS transistors with independent doublegates. International Journal of Information and Electronics Engineering. 3(1),13–15. DOI: https://doi.org/10.7763/IJIEE.2013.V3.254

[18] Nesamani, I.F.P., Raveendran, R.P.G., Prabha, V.L. (editors), 2013. Performance analysis of FinFET using various gate dielectrics. 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT); 2013 Mar 20–21; Nagercoil, India. New York: IEEE. p.761–764. DOI: https://doi.org/10.1109/ICCPCT.2013.6528831

[19] Nawaz, M., Decker, S., Giles, L.F., et al., 2008. Evaluation of process parameter space of bulk FinFETs using 3D TCAD. Microelectronic Engineering. 85(7), 1529–1539. DOI: https://doi.org/10.1016/j.mee.2008.02.014

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How to Cite

Srivastava, P., Upadhyaya, A., Yadav, S., & Negi, C. (2024). Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications. Semiconductor Science and Information Devices, 5(2), 1–10. https://doi.org/10.30564/ssid.v5i2.6075