Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

Authors

  • Pooja Srivastava

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India
  • Aditi Upadhyaya

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India
  • Shekhar Yadav

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India
  • C.M.S. Negi

    Department of Physical Sciences, Banasthali Vidyapith, Banasthali, Rajasthan, 304022, India

DOI:

https://doi.org/10.30564/ssid.v5i2.6075
Received: 19 November 2023 | Revised: 30 December 2023 | Accepted: 3 January 2024 | Published Online: 18 January 2024

Abstract

The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance, JLFET emerges as a promising alternative to CTs. Notably, JLFET lacks junctions and doping concentration gradients. In this study, the authors have conducted a comprehensive analysis and performance evaluation of JLFET and CTs, specifically in the context of low-power applications. Various performance parameters of JLFET, including SS, DIBL, transconductance, output conductance, and Ion/Ioff, have been assessed. The findings indicate that JLFET exhibits reduced susceptibility to SCEs compared to CTs and demonstrates exceptional current driving capability.

Keywords:

Short channel effects, Drain-induced barrier lowering, Subthreshold slope, Gate-all-around junction less FET, Device simulation

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How to Cite

Srivastava, P., Upadhyaya, A., Yadav, S., & Negi, C. (2024). Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications. Semiconductor Science and Information Devices, 5(2), 1–10. https://doi.org/10.30564/ssid.v5i2.6075

Issue

Vol. 5 , Iss. 2 (October 2023)

Article Type

Article

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Copyright © 2023 Pooja Srivastava, Aditi Upadhyaya, Shekhar Yadav, C.M.S. Negi

Creative Commons License

This is an open access article under the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) License.

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